The organization and operation of cache memory in

Contents Введение………………………………………………………………………………..….4 1 General characteristics and cache ....................................... ..8 1.1 Purpose cache ......................................................... 8 1.2 The development of microprocessors ......................................................... .11 1.3 Methods of the organization of the cache ............................... ......... ..14 1.4 Principles and architecture ............................................................ ..15 1.5 Multilevel memory organization .............................. ... ............ .17 1.6 registered memory ..................................................................... 18 1.7 Buffer Memory ................................................................... ...... 19 1.8 Types of cache ..................................................................... .25 2 Organization and operation of the cache memory ....................................... ... 29 2.1 Structural unit microprocessors .................................... ..29 2.2 blocks in the cache memory .................................................................. 30 2.3 Addressing the set-associative cache memory ........................ 32 2.4 Record information in the cache ................................................ 33 2.5 Architecture of single-processor Sun ................................................ 36 2.6 write-through algorithm ......................................................... ..41 2.7 Types of simple algorithms swap ................................. .42 2.8 Algorithm register swap with flags .................................... .43 2.9 Features and prospects of development of the cache ..................... ..44 3 Investigation of the effect on the performance of the size of the L2 cache ......... ................. 47 3.1 Processors of AMD ......................................................... 47 3.2 Features of the new Sempron ...................................................... ... 48 3.3 Testing the AMD processors with different L2 cache volume .......... ... .49 Заключение……………………………………………………………………………… 53 Глоссарий……………………………………………..……………………………….....52 List of sources used ............................................................ .55 Appendix A scheme of interaction processors with memory ........................ ... 58 Appendix B technology using an intermediate buffer (cache) ...... 59 Appendix B Parameters for cache workstations and servers ............ ... 60 Appendix D structure of the processor cache Pentium .............................. ..61 Appendix E Using replacement algorithm LRU .............................. ..62 Appendix E Single-processor Sun with a hierarchical memory system ............ 63 Appendix G of the primary structure of the cache 486 ........................... ... 64 Appendix H Flowchart through recording .................................... 65 The application and the results of testing in the cache SuperPi 4M .................. .66 Annex to the test results cache in 3DMark2001 SE ............ 67 Appendix A Test results cache in games ... ..68 Appendix M test results cache memory media applications ...... .69